The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 10, 2009
Filed:
Nov. 22, 2005
Susan Jane Eggers, Seattle, WA (US);
Martha Allen Mercaldi, Seattle, WA (US);
Kenneth Alan Michelson, New York, NY (US);
Mark Henry Oskin, Seattle, WA (US);
Andrew Kinoshita Petersen, Seattle, WA (US);
Andrew Richard Putnam, Seattle, WA (US);
Andrew Michalski Schwerin, Seattle, WA (US);
Steven James Swanson, Seattle, WA (US);
Susan Jane Eggers, Seattle, WA (US);
Martha Allen Mercaldi, Seattle, WA (US);
Kenneth Alan Michelson, New York, NY (US);
Mark Henry Oskin, Seattle, WA (US);
Andrew Kinoshita Petersen, Seattle, WA (US);
Andrew Richard Putnam, Seattle, WA (US);
Andrew Michalski Schwerin, Seattle, WA (US);
Steven James Swanson, Seattle, WA (US);
University of Washington, Seattle, WA (US);
Abstract
A microarchitecture and instruction set that supports multiple, simultaneously executing threads. The approach is disclosed in regard to its applicability in connection with a recently developed microarchitecture called 'WaveScalar.' WaveScalar is a compiler that breaks a control flow graph for a program into pieces called waves having instructions that are partially ordered (i.e., a wave contains no back-edges), and for which control enters at a single point. Certain aspects of the present approach are also generally applicable to executing multiple threads on a more conventional microarchitecture. In one aspect of this approach, instructions are provided that enable and disable wave-ordered memory. Additional memory access instructions bypass wave-ordered memory, exposing additional parallelism. Also, a lightweight, interthread synchronization is employed that models hardware queue locks. Finally, a simple fence instruction is used to allow applications to handle relaxed memory consistency.