The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2009

Filed:

Sep. 15, 2006
Applicants:

Kun-yi Liu, Vancouver, WA (US);

Dean Yi Liu, Vancouver, WA (US);

Inventors:

Kun-Yi Liu, Vancouver, WA (US);

Dean Yi Liu, Vancouver, WA (US);

Assignee:

Wafertech, LLC, Camas, WA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 19/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method and a computer readable medium includes instructions for obtaining time data as programmed into processing recipes or as recorded when a wafer is processed and transferred during lithography operations. The data is parsed and saved into an MES database. A report server accesses the database responsive to a query made of the database. A query may specify one or more fabrication parameters. The specified fabrication parameter or parameters is fixed and a data display is provided that compares times for processing and transferring wafers in various lithography operations used in the production of the semiconductor device and bottlenecks in lithography operations are identified by the comparative data.


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Liu, Kun-Yi. (2009). Method and software for conducting efficient lithography wph / lost time analysis in semiconductor manufacturing (U.S. Patent No. 7489982). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7489982

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