The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 10, 2009

Filed:

Dec. 10, 2004
Applicants:

Hiroyuki Ono, Kanagawa, JP;

Hiroaki Suzuki, Tokyo, JP;

Toshio Sunaga, Shiga, JP;

Hisatada Miyatake, Shiga, JP;

Hideo Asano, Tokyo, JP;

Inventors:

Hiroyuki Ono, Kanagawa, JP;

Hiroaki Suzuki, Tokyo, JP;

Toshio Sunaga, Shiga, JP;

Hisatada Miyatake, Shiga, JP;

Hideo Asano, Tokyo, JP;

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G11B 5/39 (2006.01);
U.S. Cl.
CPC ...
Abstract

In the case of magnetic head of magnetoresistance effect type whose breakdown voltage is as low as 0.3 V, it is impractical to ignore even a very small amount of static electricity that occurs during fabrication or use. In one embodiment, the desired magnetic head is produced by forming an SiOlayer on a silicon slider, thereby forming an SOI substrate; forming on the SOI substrate circuits to protect a TMR element from overvoltage and a read-write circuit; forming field effect transistors from an Si semiconductor layer (formed by reduction of the SiOlayer or epitaxial growth on the SiOlayer); forming three electrodes (source, gate, drain) on the Si semiconductor layer; forming a Schottky diode by Schottky contact (metal) with the Si semiconductor layer; forming overvoltage protective circuits of aluminum wiring on the SOI substrate; and forming a TMR element.


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