The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7489043 B1

PDF
Full Text
Expired
Date of Patent:
Feb. 10, 2009

Filed:

Oct. 18, 2006
Applicants:

Akira Tokumitsu, Miyazaki, JP;

Fumihiko Ooka, Miyazaki, JP;

Hiroshi Kawano, Miyazaki, JP;

Inventors:

Akira Tokumitsu, Miyazaki, JP;

Fumihiko Ooka, Miyazaki, JP;

Hiroshi Kawano, Miyazaki, JP;

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 23/48 (2006.01); H01L 23/52 (2006.01); H01L 29/40 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor chip package includes a first semiconductor chip, that is an MEMS chip having a movable structure. The movable structure has a movable section. The first semiconductor chip includes a plurality of first electrode pads, and a first sealing section. The first sealing section is a closed loop formed on the top face of the frame section surrounding the movable structure. The first semiconductor chip also includes a thin plate member for sealing the movable structure. The semiconductor chip package also includes a second semiconductor chip. The second semiconductor chip has a plurality of second electrode pads. The semiconductor chip package also includes a substrate. The substrate has third electrode pads. The first and second semiconductor chips are mounted on the substrate. First bonding wires connect the first electrode pads to the second electrode pads. Second bonding wires connect the second electrode pads to the third electrode pads.


Find Patent Forward Citations

Tokumitsu, Akira. (2009). Semiconductor chip package and fabrication method thereof (U.S. Patent No. 7489043). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7489043

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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