High performance integrated circuit with low skew clocking networks and improved low power operating mode having reduced recovery time

Abstract

An integrated circuit includes a phase-locked-loop with fast clock synchronization recovery. A phase frequency detector is configured to receive a system clock signal and a feedback clock signal and to generate a comparison signal. A clock generator is configured to general a first clock signal based on the comparison signal, and an internal clock signal. A controller coupled to the clock generator and configured to deliver a mesh clock signal to a global clock mesh. A synchronizer coupled to the control logic and configured to generate a feedback clock signal to the phase frequency detector. The mesh clock signal is provided from the global clock mesh to the synchronizer. Advantages of the invention include the ability to operate the integrated circuit in a sleep state with a slow clock rate and then quickly recover to an operational clock rate.