The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
May. 01, 2000
Mayank Gupta, Sunnyvale, CA (US);
Edward T. Pak, Saratoga, CA (US);
Javier Villagomez, San Jose, CA (US);
Peter H. Voss, Aromas, CA (US);
Mayank Gupta, Sunnyvale, CA (US);
Edward T. Pak, Saratoga, CA (US);
Javier Villagomez, San Jose, CA (US);
Peter H. Voss, Aromas, CA (US);
RMI Corporation, Cupertino, CA (US);
Abstract
The invention provides a cache architecture that selectively powered-up a portion of data array in a pipelined cache architecture. A tag array is first powered-up, but the data array is not powered-up during this time, to determine whether there is a tag hit from the decoded index address comparing to the tag compare data. If there is a tag hit, during a later time, a data array is then powered-up at that time to enable a cache line which corresponds with the tag hit for placing onto a data bus. The power consumed by the tag represents a fraction of the power consumed by the data array. A significant power is conserved during the time in which the tag array is assessing whether a tag hit occurs while the data array is not powered-on at this point.