The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Mar. 26, 2002
Randy L. Walter, Ada, MI (US);
John L. Schroeder, Byron Center, MI (US);
Gerald W. Vanbaren, Ada, MI (US);
Donald G. Hodges, Kentwood, MI (US);
Courtney L. Albers, Grand Rapids, MI (US);
Randy L. Walter, Ada, MI (US);
John L. Schroeder, Byron Center, MI (US);
Gerald W. Vanbaren, Ada, MI (US);
Donald G. Hodges, Kentwood, MI (US);
Courtney L. Albers, Grand Rapids, MI (US);
General Electric Company, Schnectady, NY (US);
Abstract
A computing network uses Time Division Multiplexing (TDM) to divide the time on a bus into a plurality of frames, each frame having a plurality of time slots. Each time slot is assigned no more than one of the plurality of devices within a collision domain, the assignments indicating the identity of the device permitted to transmit packets onto the network during the assigned time slot. A bus cadence unit simultaneously sends an epoch packet initiating the frame. The epoch packet contains a time slot assignment table containing the time slot assignments, the device identification, as well as a time slot offset and duration. Each device on the network is configured to measure a frame interval between repeating epoch packets. The measured frame interval is further processed in each receiving node to obtain a calibrated frame interval. The calibrated frame interval is used to accurately synchronize transmissions of data from the various devices onto the network. A time slot protocol governor in each node controls access to the bus to only the assigned time slot or slots using the calibrated frame interval to reduce or eliminate synchronization errors.