The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Mar. 31, 2004
Tsutomu Sasao, Fukuoka, JP;
Yukihiro Iguchi, Ashigarashimo-gun, JP;
Tsutomu Sasao, Fukuoka, JP;
Yukihiro Iguchi, Ashigarashimo-gun, JP;
Kitakyushu Foundation for the Advancement of Industry, Science and Technology, Kitakyushu-shi, JP;
Abstract
The PLD that can change the number of input lines and the number of rail between the memories for logic according to the objective logic function, and to which the optimum design can be done to make the size of memory minimum. The memories for logic () are arranged in series, and LUT is memorized in them. The input variables are input from the external input lines to each memories for logic (). The interconnection circuit () connects the output lines or the external input lines of memory for logic () in the preceding stage and the input lines of memory for logic () of the succeeding stage between two memories for logic (), according to the information for connection memorized in memory for interconnections (). By rewriting the information for connection according to the objective logic function, the interconnection circuit can be reconfigured, and the number of input lines and the number of rail can be changed. The size of memory can be suppressed to the minimum by optimizing the ratio of the number of rail and the number of input lines according to the logic function.