The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Feb. 03, 2009

Filed:

Oct. 02, 2002
Applicants:

Hisashi Takemura, Tokyo, JP;

Risho Koh, Tokyo, JP;

Yukishige Saito, Tokyo, JP;

Jyonu RI, Tokyo, JP;

Inventors:

Hisashi Takemura, Tokyo, JP;

Risho Koh, Tokyo, JP;

Yukishige Saito, Tokyo, JP;

Jyonu Ri, Tokyo, JP;

Assignee:

NEC Corporation, Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/772 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes a first insulating layer, a semiconductor layer formed on the first insulating layer, a second insulating layer on a part of the semiconductor layer, and a gate electrode formed on the semiconductor layer through the second insulating layer. The semiconductor layer includes a low concentration region formed under the gate electrode through the second insulating layer, two high concentration regions which are formed in at least upper regions on outer sides of the low concentration region under the gate electrode through the second insulating layer, and have an impurity concentration higher than an impurity concentration of the low concentration region, respectively, and two source/drain regions which are formed in side portions of the high concentration regions to have low concentration region side end portions, respectively. A width of the high concentration region is equal to or less than 30 nm.


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