The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Feb. 03, 2009
Filed:
Jul. 05, 2005
Huilong Zhu, Poughkeepsie, NY (US);
Brian L. Tessier, Poughkeepsie, NY (US);
Huicai Zhong, Wappingers Falls, NY (US);
Huilong Zhu, Poughkeepsie, NY (US);
Brian L. Tessier, Poughkeepsie, NY (US);
Huicai Zhong, Wappingers Falls, NY (US);
International Business Machines Corporation, Armonk, NY (US);
Advanced Micro Devices, Inc. (AMD), Sunnyvale, CA (US);
Abstract
Methods are disclosed for forming self-aligned dual stressed layers for enhancing the performance of NFETs and PFETs. In one embodiment, a sacrificial layer is used to remove a previously deposited stressed layer. A mask position used to pattern the sacrificial layer is adjusted such that removal of the latter deposited stressed layer, using the sacrificial layer, leaves the dual stress layers in an aligned form. The methods result in dual stressed layers that do not overlap or underlap, thus avoiding processing problems created by those issues. A semiconductor device including the aligned dual stressed layers is also disclosed.