Semiconductor integrated circuit, method for testing semiconductor integrated circuit, and computer readable medium for the same

Abstract

A semiconductor integrated circuit includes a random access memory; a memory BIST circuit that writes a memory test pattern into the random access memory after the random access memory passes a failure test; a scan chain which effects shift-in of a logic test pattern generated by automatic pattern generation on condition that the memory test pattern is read without being rewritten; and a combinational logic circuit that can configure a system logic circuit along with the scan chain. The random access memory outputs a data signal read from the memory test pattern, by a read command signal that is attributable to the logic test pattern and is passed the combinational logic circuit. The test result that is attributed to the read data signal and is passed through the combinational logic circuit is input to the scan chain. The scan chain shifts out the test result.