The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 27, 2009
Filed:
Jul. 26, 2006
Semiconductor integrated circuit design apparatus and semiconductor integrated circuit design method
Yoshihiro Konno, Tokyo, JP;
Yoshihiro Konno, Tokyo, JP;
NEC Corporation, Tokyo, JP;
Abstract
A semiconductor integrated circuit design method is a method for designing a semiconductor integrated circuit having a main circuit as well as the spare cell including a scan flip-flop. In the method, a net list is received, which indicates a connection relationship among circuits and their positions in a semiconductor integrated circuit. An observation point is provided in the main circuit shown in the received net list, and then an observation net list in which the observation point is provided, is created. Thereafter, the observation point is associated with a spare cell placed in the neighborhood of the observation point based on the created observation net list. A scan net list is created, in which the observation point and the scan flip-flop included in the spare cell associated with the observation point are connected to each other by wiring.