Pipelined asynchronous instruction processor having two write pipeline stages with control of write ordering from stages to maintain sequential program ordering

Abstract

A data processing circuit contains a register file () with a write port and a pipeline of instruction processing stages (-). A timing circuit () is arranged to time transfer of instruction dependent information between the stages at mutually different time points, so that processing of successive instructions in respective stages partially overlaps. A first and a second one of the stages () are in series in the pipeline. Each of the first and a second one of the stages has a result output for writing a result to the write port, if instruction dependent information in the stage concerned () requires writing. A write sequencing circuit () performs write tests alternately for instruction dependent information in the first and second one of the stages (). When the write sequencing circuit () performs the write test for a particular one of the stages (), it tests whether the instruction dependent information in the particular one of the stages () requires writing of a result. If so, the write sequencing circuit (), delays transfer of new instruction dependent information through the pipeline (-) to the particular one of the stages () until the write port has been committed to writing the result before any results that the write port is subsequently committed to write.