The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2009

Filed:

Jan. 21, 2005
Applicants:

Robert Yin, Castro Valley, CA (US);

Hamish T. Fallside, Los Gatos, CA (US);

Richard P. Burnley, Mountain View, CA (US);

Nicholas Mckay, Edinburgh, GB;

Martin B. Rhodes, Edinburgh, GB;

Douglas M. Grant, Edinburgh, GB;

Stuart A. Nisbet, Edinburgh, GB;

Gareth D. Edwards, Edinburgh, GB;

Inventors:

Robert Yin, Castro Valley, CA (US);

Hamish T. Fallside, Los Gatos, CA (US);

Richard P. Burnley, Mountain View, CA (US);

Nicholas McKay, Edinburgh, GB;

Martin B. Rhodes, Edinburgh, GB;

Douglas M. Grant, Edinburgh, GB;

Stuart A. Nisbet, Edinburgh, GB;

Gareth D. Edwards, Edinburgh, GB;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/10 (2006.01); H04L 12/28 (2006.01); H04L 12/66 (2006.01);
U.S. Cl.
CPC ...
Abstract

A media access controller system embedded in a programmable logic device is described. A platform dependent bridge for communicating with a first processor, where the platform dependent bridge is associated with a platform of the first processor and where the first processor is embedded in a programmable logic device. Host interface circuitry is coupled to the platform dependent bridge and is configured to provide a processor interface, where the processor interface is for communicating with the first processor via the platform dependent bridge and where the processor interface has a platform independent bus for communication with a second processor. At least one media access controller is coupled to the host interface circuitry.


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