The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2009

Filed:

Jun. 10, 2005
Applicants:

Yan Wang, Plano, TX (US);

Eran Pisek, Plano, TX (US);

Jasmin Oz, Plano, TX (US);

Inventors:

Yan Wang, Plano, TX (US);

Eran Pisek, Plano, TX (US);

Jasmin Oz, Plano, TX (US);

Assignee:
Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 17/15 (2006.01); G06F 7/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A re-configurable correlation unit for correlating a sequence of chip samples comprising: 1) a memory for storing the chip samples; 2) a plurality of add-subtract cells, each add-subtract cell receiving a plurality of real bits, a, and a plurality of imaginary bits, b, from a first chip sample; and 3) a plurality of sign select units. Each sign select units receives from one add-subtract cells a first input equal to a sum (a+b) of the real bits, a, and the imaginary bits, b, and a second input equal to a difference (a−b) of the real bits, a, and the imaginary bits, b. Each sign select unit generates a real output and an imaginary output, wherein each of the real and imaginary outputs is equal to one of: 1) the sum (a+b) multiplied by one of +1 and −1 and 2) the difference (a−b) multiplied by one of +1 and −1.


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