Semiconductor memory device capable of checking a redundancy code and memory system and computer system having the same

Abstract

Semiconductor memory devices include a memory cell array, a deserializer, a decoder, a redundancy code checker, a control circuit, a redundancy code generator and a serializer. The deserializer generates a deserialized data by deserializing a first serialized data. The decoder generates a first data, a command signal, an address signal and a first redundancy code by decoding the deserialized data. The redundancy code checker generates a status signal by comparing the first data with the first redundancy code and detects an error in the first data. The control circuit stores the first data in the memory cell array or outputs a second data stored in the memory cell array in response to the command signal and the address signal. The redundancy code generator generates a second redundancy code by using the second data. The serializer generates a second serialized data by serializing the second data and the second redundancy code.