The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 27, 2009

Filed:

May. 10, 2006
Applicants:

Tapan Jyoti Chakraborty, West Windsor, NJ (US);

Aditya Jagirdar, Highland Park, NJ (US);

Roystein Oliveira, Highland Park, NJ (US);

Inventors:

Tapan Jyoti Chakraborty, West Windsor, NJ (US);

Aditya Jagirdar, Highland Park, NJ (US);

Roystein Oliveira, Highland Park, NJ (US);

Assignees:

Alcatel-Lucent USA Inc., Murray Hill, NJ (US);

Rutgers, The State University of New Jersey, New Brunswick, NJ (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H03K 19/003 (2006.01);
U.S. Cl.
CPC ...
Abstract

A register designed to detect and correct soft errors in real time. A redundant latch is added to the existing structure of a flip flop and functional data is simultaneously registered at multiple latches. The content of these multiple latches are fed to a majority voting circuit. If the content of any of these latches is corrupted by soft error, it is filtered out through the majority voting circuit and correct data is passed out from the output of the flip flop. In one embodiment, this design operates as a simple scan flip flop or scan-hold flip flop, and is useful for system testability purposes.


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