Integrated circuit with testable clock circuits

Abstract

An integrated circuit () that comprises an internal clock circuit () with a clock output for clocking functional circuits () of the integrated circuit (). The integrated circuit is provided with a counter circuit () and a state holding circuit () for use during testing. The integrated circuit is switched to a test mode and a start of a test time interval is signalled. Clock pulses from the internal clock circuitare counted from the start of the test time interval and the state holding circuit () is locked into a predetermined state if the internal clock circuit has produced more than a predetermined number of clock pulses from the start of the test time interval. Information about whether the state holding circuit () has reached the predetermined state in the test time interval is read from the integrated circuit () and the information is used by a test evaluation apparatus () to accept or reject the integrated circuit ().