The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2009
Filed:
Apr. 16, 2003
Eric J. Crabill, San Jose, CA (US);
Eric J. Crabill, San Jose, CA (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
Methods and cores using an existing processor implemented in a Programmable Logic Device (PLD) to emulate a target processor, where the existing and target processors support different instruction sets and conform to different bus interface protocols. A bus interface unit is coupled to an existing processor in a PLD. The bus interface unit is implemented using the programmable logic resources of the PLD, while the existing processor can be a dedicated processor or an existing 'soft' processor. The bus interface unit acts as a peripheral device to translate bus transactions from the existing bus protocol (i.e., the bus protocol understood by the existing processor) to the target bus protocol. In addition, a stored emulation program emulates the target instruction set while executing instructions using the instruction set supported by the existing processor.