Method of finding data dependent timing and voltage jitter for different bits in an arbitrary digital signal in accordance with selected surrounding bits

Abstract

Separation and analysis of measured Total Jitter (TJ) begins with a suitably long arbitrary digital test pattern, from which an Acquisition Record is made. A Time Interval Error (TIE) or Voltage Level Error (VLE) Record is made of the Acquisition Record. A Template defines a collection of associated bit value or transitions that are nearby or otherwise related to a bit location of interest, and has associated therewith a collection of Descriptors and their respective Metrics. Each Descriptor identifies one of the various different patterns of bit value or transitions that fit the Template. The TIE/VLE Record is examined, and a parameter is measured for each instance of each Descriptor for the Template. The collection of measured parameters for each particular Descriptor are combined (e.g., averaging) to produce the Metric for that Descriptor. A Look-Up Table (LUT) addressed by the different possible Descriptors is loaded with the associated discovered Metric, which is a plausible value for Data Dependent Jitter (DDJ) at that bit. DDJ separates from TJ because DDJ is correlated with the Descriptors, while Periodic Jitter (PJ) and Random Jitter (RJ) can be expected to average to near zero over a sufficient number of instances of a given Descriptor. Identified instances of DDJ are individually removed from corresponding locations of TJ found for the entire waveform (the original TIE/VLE Record) to leave an Adjusted TIE/VLE Record that is PJ convolved with RJ.