The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 20, 2009

Filed:

Feb. 21, 2006
Applicants:

Eric Scheuerlein, Los Gatos, CA (US);

Donald M. Archer, Santa Clara, CA (US);

Inventors:

Eric Scheuerlein, Los Gatos, CA (US);

Donald M. Archer, Santa Clara, CA (US);

Assignee:

National Semiconductor Corporation, Santa Clara, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G11C 7/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

An embodiment of the present invention is directed to a circuit for indicating the program status of an EPROM. The circuit includes a first and second transistor coupled to a first voltage potential. The circuit further includes a latching circuit coupled to the first and second transistors. The latching circuit outputs a first output value when the current through the first transistor is greater than the current through the second transistor and a second output value when less. The circuit further includes a capacitive element coupled between a gate of the first transistor and a third voltage potential, the capacitance of the capacitive element being such that the output of the latching circuit is always a first digital state prior to programming the EPROM and a second digital state after programming the EPROM.


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