The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 20, 2009
Filed:
Sep. 28, 2006
Paul F. Illegems, Tucson, AZ (US);
Srinivas Pulijala, Tucson, AZ (US);
Paul F. Illegems, Tucson, AZ (US);
Srinivas Pulijala, Tucson, AZ (US);
Standard Microsystems Corporation, Hauppauge, NY (US);
Abstract
A three-level detector circuit may comprise an input node and a pair of diode-connected transistors having respective drain terminals coupled to the input node. The pair of diode-connected transistors may be configured to set a voltage if the input voltage at the input node corresponds to an open input. The three-level detector circuit may further comprise a pair of inverting stages coupled to the input node, the pair of inverting stages configured to distinguish between low, high, and/or open inputs. The three-level detector circuit may also comprise a pair of latches, e.g. D-flip-flops, each of the pair of latches having a respective input coupled to a respective output of a respective one of the pair of inverting stages, and each of the pair of latches configured to latch a present state of the input in detection mode. In one set of embodiments, the three-level detector circuit is operable to cease conducting current after the present state of the input has been latched.