The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7477636 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 13, 2009

Filed:

Nov. 26, 2003
Applicants:

Asif Q. Khan, Austin, TX (US);

David B. Kramer, Austin, TX (US);

David P. Sonnier, Austin, TX (US);

Inventors:

Asif Q. Khan, Austin, TX (US);

David B. Kramer, Austin, TX (US);

David P. Sonnier, Austin, TX (US);

Assignee:

Agere Systems Inc., Allentown, PA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H04B 7/212 (2006.01);
U.S. Cl.
CPC ...
Abstract

A processor includes a scheduler operative to schedule data blocks for transmission from a plurality of queues or other transmission elements, utilizing at least a first table and a second table. The first table may comprise at least first and second first-in first-out (FIFO) lists of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a first scheduling algorithm, such as a weighted fair queuing scheduling algorithm. The scheduler maintains a first table pointer identifying at least one of the first and second lists of the first table as having priority over the other of the first and second lists of the first table. The second table includes a plurality of entries corresponding to transmission elements for which data blocks are to be scheduled in accordance with a second scheduling algorithm, such as a constant bit rate or variable bit rate scheduling algorithm.


Find Patent Forward Citations

Khan, Asif. (2009). Processor with scheduler architecture supporting multiple distinct scheduling algorithms (U.S. Patent No. 7477636). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7477636

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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