The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2009
Filed:
Aug. 31, 2006
Ronald A. Kapusta, Jr., Waltham, MA (US);
Ronald A. Kapusta, Jr., Waltham, MA (US);
Analog Devices, Inc., Norwood, MA (US);
Abstract
In one embodiment, a circuit comprises at least first and second circuit stages, at least one level shifting circuit, and a control circuit. The first circuit stage is configured and arranged to produce a reference voltage at the at least one first output during each first phase of at least first and second phases, and to produce an output signal at the at least one first output that is responsive to an input signal at the at least one first input during each second phase of the at least first and second phases. The at least one level shifting circuit comprises at least one capacitor and at least one switch and is coupled between the first circuit stage and the second circuit stage. The control circuit is configured to control the level shifting circuit such that, during each first phase, respective plates of the at least one capacitor are connected to the at least one first output of the first circuit stage and a source of a substantially constant voltage so as to allow the at least one capacitor to be charged to a level-shift voltage equal to a difference between the substantially constant voltage and the reference voltage, and such that, during each second phase, the respective plates of the at least one capacitor are connected to the at least one first output and the at least one second input to thereby introduce the level-shift voltage across the at least one capacitor as an offset voltage therebetween.