The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 13, 2009
Filed:
Jun. 16, 2006
Tim Tuan, San Jose, CA (US);
Arifur Rahman, San Jose, CA (US);
Satyaki Das, Los Gatos, CA (US);
Sean W. Kao, South Pasadena, CA (US);
Tim Tuan, San Jose, CA (US);
Arifur Rahman, San Jose, CA (US);
Satyaki Das, Los Gatos, CA (US);
Sean W. Kao, South Pasadena, CA (US);
XILINX, Inc., San Jose, CA (US);
Abstract
A PLD utilizes a heterogeneous architecture to reduce power consumption of its active resources. The PLD's programmable resources are divided into a first partition and a second partition, where the resources of the first partition are optimized for low power consumption and the resources of the second partition are optimized for high performance. Portions of a user design containing non-critical timing paths are mapped to and implemented by the resources of the power-optimized first partition, and portions of the user design containing critical timing paths are mapped to and implemented by the resources of the performance-optimized second partition.