Method of fabricating a semiconductor device with a bit line contact plug

Abstract

In one embodiment, a semiconductor device includes a plurality of gate electrodes formed on a semiconductor substrate including a cell region, a core region, and a peripheral circuit region, along with source/drain regions. A first landing pad contacts the source/drain of the cell region. A second landing pad contacts the source/drain of an NMOS of the core region. A first, second, third, and fourth contact plug, each surrounded by spacers, respectively contact the first landing pad, the second landing pad, the source/drain of a PMOS of the core region, and the source/drain of the peripheral circuit region. Also, a fifth and sixth contact plug, respectively contact the source/drain of the NMOS of the peripheral circuit region and the gate conductive layer included in the gate electrode of the peripheral circuit region.