The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Dec. 06, 2005
Applicants:
Shuhsaku Matsuse, Kusatsu, JP;
Makoto Ueda, Kyoto, JP;
Inventors:
Shuhsaku Matsuse, Kusatsu, JP;
Makoto Ueda, Kyoto, JP;
Assignee:
International Business Machines Corporation, Armonk, NY (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 13/16 (2006.01); G06F 13/28 (2006.01); G06F 13/00 (2006.01); G06F 15/76 (2006.01);
U.S. Cl.
CPC ...
Abstract
A mixed architecture system on chip is provided by combining a CoreConnect system on chip architecture with an AMBA system on chip architecture. To eliminate data transfer and bus error that could occur in the mixed architecture, an additional peripheral bus and bridge are provided to manage communication with AHB resources.
Matsuse, Shuhsaku. (2009). System-on-a-chip mixed bus architecture (U.S. Patent No. 7475182). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7475182
Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile