The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Jun. 15, 2005
Deboleena Minz, New Delhi, IN;
Deboleena Minz, New Delhi, IN;
STMicroelectronics Pvt. Ltd., Uttar Pradesh, IN;
Abstract
A one bit full adder with sum and carry outputs performs independent functions. The full adder includes at least one look up table (LUT) for implementing a sum function, and at least one carry circuit for implementing a carry/borrow function. The carry circuit includes a first multiplexer having first and second inputs, a select line input, and a carry/borrow output. The carry circuit also includes an AND gate, an OR gate and an XOR gate. The AND gate has two inputs, and an output connected to the first input of the first multiplexer. The OR gate has two inputs, and an output connected to the second input of the first multiplexer. The XOR gate has a first input, and an output connected to the select line input of the first multiplexer. A second multiplexer has an output connected to the first input of the XOR gate. The at least one LUT and the at least one carry circuit provides independent sum and carry outputs for different function requirements.