The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2009

Filed:

Sep. 29, 2003
Applicants:

Fred Gehrung Gustavson, Briarcliff Manor, NY (US);

John A. Gunnels, Mt. Kisco, NY (US);

Inventors:

Fred Gehrung Gustavson, Briarcliff Manor, NY (US);

John A. Gunnels, Mt. Kisco, NY (US);

Attorneys:
Primary Examiner:
Int. Cl.
CPC ...
G06F 15/00 (2006.01); G06F 7/52 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method (and structure) of improving at least one of speed and efficiency when executing a linear algebra subroutine on a computer having a memory hierarchical structure including at least one cache, the computer having M levels of caches and a main memory. Based on sizes, it is determined, for a level 3 matrix multiplication processing, which matrix will have data for a submatrix block residing in a lower level cache of the computer and which two matrices will have data for submatrix blocks residing in at least one higher level cache or a memory. From a plurality of six kernels, two kernels are selected as optimal to use for executing the level 3 matrix multiplication processing as data streams from different levels of the M levels of cache, such that the processor will switch back and forth between the two selected kernels as streaming data traverses the different levels of cache. Data from the selected two matrices is streamed, for executing the level 3 matrix multiplication processing, so that the submatrix block residing in the lower level cache remains resident in the lower level cache.


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