The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Apr. 17, 2007
Perry H. Pelly, Austin, TX (US);
Carlos A. Greaves, Austin, TX (US);
Perry H. Pelly, Austin, TX (US);
Carlos A. Greaves, Austin, TX (US);
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A memory () has a plurality of memory cells, a serial address port () for receiving a low voltage high frequency differential address signal, and a serial input/output data port () for receiving a high frequency low voltage differential data signal. The memory () can operate in one of two different modes, a normal mode and a cache line mode. In cache line mode, the memory can access an entire cache line from a single address. A fully hidden refresh mode allows for timely refresh operations while operating in cache line mode. Data is stored in the memory array () by interleaving in multiple sub-arrays (). During a hidden refresh mode of operation, one sub-array () is accessed while another sub-array () is refreshed. Two or more of the memories () may be chained together to provide a high speed low power memory system.