The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
May. 08, 2007
Stanley Wang, Cupertino, CA (US);
Thomas H. Lee, Burlingame, CA (US);
Stanley Wang, Cupertino, CA (US);
Thomas H. Lee, Burlingame, CA (US);
ZeroG Wireless, Inc., Sunnyvale, CA (US);
Abstract
A calibration circuit () for calibrating a frequency synthesizer () having a voltage-controlled oscillator (VCO) () with a plurality of switched-capacitor arrays (CA-CAn). The calibration circuit () counts a predetermined number of periods of the reference-clock signal (ref_clk) and divide-clock signal (div_clk) of the frequency synthesizer using a fast clock signal (fastclk). The fast-clock signal (fastclk) has a frequency greater than either the reference-clock signal (ref_clk) or the divide-clock signal (div_clk), enabling significantly faster calibration of the frequency synthesizer () than would be possible using the reference-clock signal (ref_clk). The calibration circuit () compares the count of the periods of the reference-clock signal (ref_clk) and the divide-clock signal (div_clk) and varies the tank signal of the VCO (VCO_tank_setting) until the count of the periods is substantially equal.