The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7473962 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 06, 2009

Filed:

Jan. 12, 2006
Applicants:

Yutaka Maruo, Sakata, JP;

Susumu Inoue, Atsugi, JP;

Yo Takeda, Shonai, JP;

Inventors:

Yutaka Maruo, Sakata, JP;

Susumu Inoue, Atsugi, JP;

Yo Takeda, Shonai, JP;

Assignee:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 29/94 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor device includes: a semiconductor layer; a first area and a second area which are demarcated by a separation insulating layer provided on the semiconductor layer; a nonvolatile memory provided on the first area; a plurality of MOS transistors provided on the second area; a first interlayer insulating layer embedded between the plurality of MOS transistors on the second area; and a second interlayer insulating layer provided above the first area and the second area. The second interlayer insulating layer is provided as if covering the nonvolatile memory on the first area and, on the second area, provided, being above the first interlayer insulating layer, as if covering the MOS transistor.


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