The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Jan. 06, 2009

Filed:

Apr. 22, 2007
Applicants:

Shian-hau Liao, Tai-Chung, TW;

Tsung-shin Wu, Kao-Hsiung, TW;

Chih-chiang Kuo, Taipei, TW;

Chien-li Cheng, Hsin-Chu, TW;

Inventors:

Shian-Hau Liao, Tai-Chung, TW;

Tsung-Shin Wu, Kao-Hsiung, TW;

Chih-Chiang Kuo, Taipei, TW;

Chien-Li Cheng, Hsin-Chu, TW;

Assignee:

Nanya Technology Corp., Kueishan, Tao-Yuan Hsien, TW;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/8242 (2006.01); H01L 21/20 (2006.01); H01L 21/4763 (2006.01);
U.S. Cl.
CPC ...
Abstract

A method for forming a stack capacitor includes providing a substrate with a bottom layer, a BPSG layer, a USG layer and a top layer thereon; using the top layer as a hard mask and the substrate as a first etching stop layer to perform a dry etching process to form a tapered trench in the bottom layer, the BPSG layer and the USG layer; removing the top layer to perform a selective wet etching process to partially remove the BPSG layer; depositing conformally a poly-Si layer and filling the trench with a sacrificial layer; removing the poly-Si layer unmasked by the sacrificial layer; using the bottom layer as a second etching stop layer to perform a wet etching process to remove the USG layer and BPSG layer; performing a static drying process; and depositing a dielectric layer and a conductive material to form the stack capacitor.


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