The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Jan. 06, 2009
Filed:
Sep. 03, 2007
Wai Yew Lo, Selangor, MY;
Heng Keong Yip, Selangor, MY;
Wai Yew Lo, Selangor, MY;
Heng Keong Yip, Selangor, MY;
Freescale Semiconductor, Inc., Austin, TX (US);
Abstract
A flip-chip bump carrier type package is formed by providing a sheet of metal foil and forming cavities in a first surface of the sheet. The cavities are plated with a conductive metal to form external interconnects. An insulating film is formed over the metal foil first surface and the plated cavities and then vias are formed in the insulating film. The vias contact respective ones of the plated cavities. The vias are then plated and a solder resist film is formed over the insulating film and the plated vias. The solder resist film is processed to form exposed areas above the vias, which areas are then plated with a conductive metal. A bumped semiconductor die is attached to the first surface of the metal foil, where the die bumps contact respective ones of the plated, exposed areas, which electrically connects the die to the plated cavities. Finally, the sheet of metal foil is removed so that outer surfaces of the plated cavities are exposed. As stated above, the plated cavity outer surfaces form electrical interconnects between the die and a printed wiring board.