The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Patent No.:

US 7473319 B1

PDF
Full Text
Expired
Date of Patent:
Jan. 06, 2009

Filed:

Aug. 09, 2005
Applicant:

Kazunari Kimino, Hyogo-ken, JP;

Inventor:

Kazunari Kimino, Hyogo-ken, JP;

Assignee:

Ricoh Company, Ltd., Tokyo, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 23/525 (2006.01);
U.S. Cl.
CPC ...
Abstract

An apparatus and a method for manufacturing semiconductor devices is disclosed for selectively disconnecting a fuse element out of plural fuse elements formed on a semiconductor wafer substrate which is provided with the plural fuse elements and a dielectric layer having at least one opening corresponding to the location for the plural fuse elements. The method includes processing steps implemented onto the wafer substrate, such as (a) forming a layer of etching barrier resin by scanning at least one discharging nozzle for discharging the raw etching barrier resin while suitably discharging droplets of raw etching barrier resin to replenish the opening corresponding to the location of the fuse element not to be disconnected, (b) hardening the raw etching barrier resin to be a layer of etching barrier resin, and (c) the fuse element in the prescribed disconnecting area without overlying portion of the etching barrier resin layer is selectively disconnected by etching using the dielectric layer and the etching barrier resin as a mask.


Find Patent Forward Citations

Kimino, Kazunari. (2009). Apparatus and method for manufacturing semiconductor device incorporating fuse elements (U.S. Patent No. 7473319). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7473319

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