The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2008

Filed:

Mar. 29, 2004
Applicants:

Jerome J. Cartmell, Natick, MA (US);

Qun Fan, Boston, MA (US);

Steven T. Mcclure, Northboro, MA (US);

Robert Decrescenzo, Franklin, MA (US);

Haim Kopylovitz, Newton, MA (US);

Eli Shagam, Brookline, MA (US);

Inventors:

Jerome J. Cartmell, Natick, MA (US);

Qun Fan, Boston, MA (US);

Steven T. McClure, Northboro, MA (US);

Robert DeCrescenzo, Franklin, MA (US);

Haim Kopylovitz, Newton, MA (US);

Eli Shagam, Brookline, MA (US);

Assignee:

EMC Corporation, Hopkinton, MA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 12/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Accessing data memory includes writing data to a first memory location and to a second memory location in response to a request to write data to a memory address that corresponds to both locations, where the first and second memory locations are mirrored, in response to a request to read data from the memory address, reading data from the first memory location or the second memory location based on load balancing, and accessing data from the second memory location in response to a request to access data at the memory address when memory hardware corresponding to the first memory location has failed. Accessing the data memory may include requesting access to a specific one of the first and second memory locations. The memory address may contain a portion that is common to both the first memory location and the second memory location. Hardware coupled to the memory may cause data written using the memory address to be automatically written to the first memory location and the second memory location.


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