Mixer with clock resynchronization and method therefor

Abstract

A mixer () includes a phase clock generator (), a latch (), and a multiplier (). The phase clock generator () provides a plurality of phase clock signals. The latch () is coupled to the phase clock generator () via a first plurality of conductors () and provides a plurality of resynchronized phase clock signals. The multiplier () is coupled to the latch () via a second plurality of conductors () and mixes an input signal using the plurality of resynchronized phase clock signals to provide a mixed output signal. The second plurality of conductors () is characterized as having a lower end-to-end impedance than an end-to-end impedance of the first plurality of conductors ().