The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 30, 2008

Filed:

Mar. 31, 2008
Applicant:

Manoj Chirania, Palo Alto, CA (US);

Inventor:

Manoj Chirania, Palo Alto, CA (US);

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H03K 19/173 (2006.01);
U.S. Cl.
CPC ...
Abstract

Lookup table circuits (LUTS) having multiple stages differently optimized to balance delays through the lookup table. A first multiplexing stage is optimized for a fast path from the control input to the data outputs, while a second and subsequent stage multiplexers are optimized for a fast path from data inputs to data outputs. In some embodiments, additional delay is introduced into the control inputs of the later stages, e.g., the LUT input paths with the smallest through-delays, in order to further balance the through-delays for the lookup table.


Find Patent Forward Citations

Chirania, Manoj. (2008). Lookup table with relatively balanced delays (U.S. Patent No. 7471104). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7471104

Data source: USPTO (United States Patent and Trademark Office) public patent records. Weekly synchronization. How IDiyas builds this profile

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