The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 30, 2008
Filed:
Feb. 18, 2005
Jong-jan Lee, Camas, WA (US);
Jer-shen Maa, Vancouver, WA (US);
Douglas J. Tweet, Camas, WA (US);
Yoshi Ono, Camas, WA (US);
Sheng Teng Hsu, Camas, WA (US);
Jong-Jan Lee, Camas, WA (US);
Jer-Shen Maa, Vancouver, WA (US);
Douglas J. Tweet, Camas, WA (US);
Yoshi Ono, Camas, WA (US);
Sheng Teng Hsu, Camas, WA (US);
Sharp Laboratories of America, Inc., Camas, WA (US);
Abstract
A method of making CMOS devices on strained silicon on glass includes preparing a glass substrate, including forming a strained silicon layer on the glass substrate; forming a silicon oxide layer by plasma oxidation of the strained silicon layer; depositing a layer of doped polysilicon on the silicon oxide layer; forming a polysilicon gate; implanting ions to form a LDD structure; depositing and forming a spacer dielectric on the gate structure; implanting and activation ions to form source and drain structures; depositing a layer of metal film; annealing the layer of metal film to form salicide on the source, drain and gate structures; removing any unreacted metal film; depositing a layer of interlayer dielectric; and forming contact holes and metallizing.