The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 23, 2008
Filed:
Aug. 30, 2006
Circuit for and method of generating a delay in an input/output port of an integrated circuit device
Venu Kondapalli, Sunnyvale, CA (US);
Prasad Rau, Saint Louis, MO (US);
Venu Kondapalli, Sunnyvale, CA (US);
Prasad Rau, Saint Louis, MO (US);
Xilinx, Inc., San Jose, CA (US);
Abstract
A circuit for generating a delayed output in an input/output port of a device adapted to implement circuits operating on a range of voltages is disclosed. The circuit comprises a first terminal of a delay stage of said input/output port coupled to receive a signal to be output by the circuit; a first pass gate coupled to the first terminal; a capacitor having a first terminal coupled to the output of the first pass gate and a second terminal coupled to ground; a second pass gate coupled to the first terminal of the capacitor; and a second terminal of said delay stage of said input/output port coupled to the second pass gate and outputting a delayed signal based upon the second pass gate. A method of generating a delayed output in an input/output stage of a device adapted to implement circuits operating on a range of voltages is also disclosed.