The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2008
Filed:
Oct. 07, 2005
David T. Price, Gresham, OR (US);
Jayashree Kalpathy-cramer, West Linn, OR (US);
Mark Ward, West Linn, OR (US);
David T. Price, Gresham, OR (US);
Jayashree Kalpathy-Cramer, West Linn, OR (US);
Mark Ward, West Linn, OR (US);
LSI Corporation, Milpitas, CA (US);
Abstract
A method for verifying that a physical location of a memory matches a design logical representation, without having to use a focused ion beam to physically damage a memory location. The method provides that either a temporary or permanent circuit 'defect' is intentionally created in the physical layout. Then, the new electrical schematic is extracted from the modified physical layout. Subsequently, if the design 'defect' which was created is temporary, the new electrical schematic is simulated, the logical address of the “defect” is determined, and the extracted logical address is compared to the expected address to verify the logical to physical correlation. Alternatively, if the design “defect” which was created is permanent, after the new electrical schematic is extracted from the modified physical layout, the product is fabricated and the known design “defect” location is used to correlate to the electrically-tested defect logical location.