The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2008

Filed:

Apr. 11, 2005
Applicants:

Toshikazu Nakamura, Kawasaki, JP;

Akira Kikutake, Kawasaki, JP;

Kuninori Kawabata, Kawasaki, JP;

Yasuhiro Onishi, Kawasaki, JP;

Satoshi Eto, Kawasaki, JP;

Inventors:

Toshikazu Nakamura, Kawasaki, JP;

Akira Kikutake, Kawasaki, JP;

Kuninori Kawabata, Kawasaki, JP;

Yasuhiro Onishi, Kawasaki, JP;

Satoshi Eto, Kawasaki, JP;

Assignee:

Fujitsu Limited, Kawasaki, JP;

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 11/00 (2006.01);
U.S. Cl.
CPC ...
Abstract

Disclosed is a semiconductor memory device capable of arbitrarily setting an upper limit of the number of error corrections during a test operation. The semiconductor memory device has a counter, a register, and a comparison circuit. The counter counts the number of error corrections. The register, when an upper limit setting signal is externally inputted to change the upper limit of the number of error corrections, changes the upper limit. The comparison circuit compares the number of error corrections with the changed upper limit.


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