The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2008

Filed:

Jan. 21, 2005
Applicants:

Ting Yun Kao, Cupertino, CA (US);

Robert Yin, Castro Valley, CA (US);

Richard P. Burnley, Mountain View, CA (US);

Nicholas Mckay, Edinburgh, GB;

Martin B. Rhodes, Edinburgh, GB;

Inventors:

Ting Yun Kao, Cupertino, CA (US);

Robert Yin, Castro Valley, CA (US);

Richard P. Burnley, Mountain View, CA (US);

Nicholas McKay, Edinburgh, GB;

Martin B. Rhodes, Edinburgh, GB;

Assignee:

Xilinx, Inc., San Jose, CA (US);

Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 1/00 (2006.01); G06F 1/04 (2006.01);
U.S. Cl.
CPC ...
Abstract

A clock interface for a media access controller in a programmable logic device is described. The media access controller includes a clock generator for providing a clock signal to configured configurable routing of the programmable logic device to obtain a loaded version thereof. The loaded clock signal is provided to a clock network of the media access controller and to a delay cell of the media access controller to obtain an indication of the loading by the user instantiated design.


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