The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2008

Filed:

Feb. 20, 2004
Applicants:

Leon Zheng, San Jose, CA (US);

Martin Langhammer, Alderbury, GB;

Steven Perry, High Wycombe, GB;

Paul Metzgen, Chiswick, GB;

Nitin Prasad, Milpitas, CA (US);

William Hwang, Fremont, CA (US);

Inventors:

Leon Zheng, San Jose, CA (US);

Martin Langhammer, Alderbury, GB;

Steven Perry, High Wycombe, GB;

Paul Metzgen, Chiswick, GB;

Nitin Prasad, Milpitas, CA (US);

William Hwang, Fremont, CA (US);

Assignee:

Altera Corporation, San Jose, CA (US);

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
G06F 7/38 (2006.01);
U.S. Cl.
CPC ...
Abstract

Saturation and rounding capabilities are implemented in multiply-accumulate (MAC) blocks to provide rounded and saturated outputs of multipliers and of add-subtract-accumulate circuits implemented using DSP. These features support any suitable format of value representation, including the x.15 format. Circuitry within the multipliers and the add-subtract-accumulate circuits implement the rounding and saturation features of the present invention.


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