Level shifter circuit and method for controlling voltage levels of clock signal and inverted clock signal for driving gate lines of amorphous silicon gate-thin film transistor liquid crystal display

Abstract

Provided are a level shifter circuit and a corresponding method for controlling voltage levels of a clock signal and an inverted clock signal for driving gate lines of a ASG thin film transistor liquid crystal display panel, where the level shifter circuit includes first and second level shifters, the first level shifter controls the voltage level of the clock signal to swing between a negative external voltage level and a positive external voltage level in response to a clock activating signal, and increases the voltage level of the clock signal from the negative external voltage level to a power supply voltage level or decreases it from the positive external voltage level to a ground voltage level while a pre-charge clock activating signal is activated, the second level shifter controls the voltage level of the inverted clock signal to swing between the negative external voltage level and the positive external voltage level in response to an inverted clock activating signal, and increases the voltage level of the inverted clock signal from the negative external voltage level to the power supply voltage level or decreases it from the positive external voltage level to the ground voltage level while an inverted pre-charge clock activating signal is activated, and the level shifter circuit increases or decreases the voltage levels of the clock signal and inverted clock signal using a battery voltage or a ground voltage, thereby reducing current consumption caused by the increase or decrease in the voltage level.