The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 16, 2008
Filed:
Dec. 05, 2007
Lakhbeer S. Sidhu, San Jose, CA (US);
Irfan Rahim, San Jose, CA (US);
Jeffrey Watt, Palo Alto, CA (US);
John Turner, Santa Cruz, CA (US);
Lakhbeer S. Sidhu, San Jose, CA (US);
Irfan Rahim, San Jose, CA (US);
Jeffrey Watt, Palo Alto, CA (US);
John Turner, Santa Cruz, CA (US);
Altera Corporation, San Jose, CA (US);
Abstract
A configuration memory cell ('CRAM') for a field programmable gate array ('FPGA') integrated circuit (“IC”) device is given increased resistance to single event upset (“SEU”). A portion of the gate structure of the input node of the CRAM is increased in size relative to the nominal size of the remainder of the gate structure. Part of the enlarged gate structure is located capacitively adjacent to an N-well region of the IC, and another part is located capacitively adjacent to a P-well region of the IC. This arrangement gives the input node increased capacitance to resist SEU, regardless of the logical level of the input node. The invention is also applicable to any node of any type of memory cell for which increased resistance to SEU is desired.