The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2008

Filed:

May. 10, 2006
Applicants:

Jeng-huang Wu, Taipei, TW;

Chiung-yu Feng, Hsin-Chu Hsien, TW;

Chien-chih Huang, Chiayi, TW;

Yu-wen Tsai, Hsin-Chu, TW;

Inventors:

Jeng-Huang Wu, Taipei, TW;

Chiung-Yu Feng, Hsin-Chu Hsien, TW;

Chien-Chih Huang, Chiayi, TW;

Yu-Wen Tsai, Hsin-Chu, TW;

Assignee:

Faraday Technology Corp., Science Based Industrial Park, Hsin-Chu, TW;

Attorney:
Primary Examiner:
Int. Cl.
CPC ...
H01L 27/02 (2006.01); H01L 27/10 (2006.01);
U.S. Cl.
CPC ...
Abstract

A semiconductor layout includes a p substrate, a first semiconductor cell formed over the p substrate, and a second semiconductor cell formed over the p substrate adjacent to the first semiconductor cell. A total height of the first semiconductor cell and the second semiconductor cell is twice a height of a standard semiconductor cell, and the height of the second semiconductor cell is adjusted according to the height of the first semiconductor cell.


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