The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.

The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.

Date of Patent:
Dec. 16, 2008

Filed:

Mar. 14, 2005
Applicant:

Yves-matthieu Le Vaillant, Crolles, FR;

Inventor:
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
H01L 21/30 (2006.01);
U.S. Cl.
CPC ...
Abstract

Methods for fabricating a wafer structure having a strained silicon utility layer are described. In an embodiment, the method includes providing a prototype wafer having at least a support substrate and a strained silicon model layer upon the support substrate, and then providing a relaxed silicon-germanium layer on the strained silicon model layer. Next, a strained silicon utility layer is provided on the relaxed silicon-germanium layer to form an intermediate structure. The strained silicon utility layer has substantially the same characteristics as the strained silicon model layer. The method also includes detaching the strained silicon utility layer from the intermediate structure at a predetermined zone of weakness in the relaxed silicon-germanium layer to form a wafer structure having a strained silicon utility layer.


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