The patent badge is an abbreviated version of the USPTO patent document. The patent badge does contain a link to the full patent document.
The patent badge is an abbreviated version of the USPTO patent document. The patent badge covers the following: Patent number, Date patent was issued, Date patent was filed, Title of the patent, Applicant, Inventor, Assignee, Attorney firm, Primary examiner, Assistant examiner, CPCs, and Abstract. The patent badge does contain a link to the full patent document (in Adobe Acrobat format, aka pdf). To download or print any patent click here.
Patent No.:
Date of Patent:
Dec. 09, 2008
Filed:
Aug. 11, 2006
Applicant:
Min-fang Ho, San Jose, CA (US);
Inventor:
Min-Fang Ho, San Jose, CA (US);
Assignee:
Xilinx, Inc., San Jose, CA (US);
Attorney:
Primary Examiner:
Assistant Examiner:
Int. Cl.
CPC ...
G06F 17/50 (2006.01);
U.S. Cl.
CPC ...
Abstract
A method of verifying a layout of an integrated circuit device is disclosed. The method comprises steps of receiving a physical layout for a schematic of a circuit implemented in the integrated circuit device; generating an implant table file having data showing a relationship between layers and device types of the integrated circuit device; and generating a layout-versus-schematic rules file using the implant table file.
Ho, Min-Fang. (2008). Method of and circuit for verifying a layout of an integrated circuit device (U.S. Patent No. 7464350). U.S. Patent and Trademark Office. https://idiyas.com/patent/badge/7464350
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