Shift register, scanning line driving circuit, matrix type device, electro-optic device, and electronic device

Abstract

The invention provides a shifter register comprising: a plurality of shift circuit blocks connected in series, each of which includes a predetermined even-number of shift unit circuits; a plurality of clock decision circuit, each of which is provided for each of a plurality of the shift circuit blocks and receives internal condition signals from even-numbered shift unit circuits included in a corresponding shift circuit block and an internal condition signal from the last shift unit circuit included in a preceding shift circuit block, each of the clock decision circuit outputting an operation allowance signal when at least one of the internal condition signals has a first level; and a plurality of clock control circuits, each of which is provided for each of a plurality of the shift circuit blocks and performs a clock signal output operation when the operation allowance signal is supplied from a corresponding clock decision circuit commonly connected to another shift circuit block.